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MT9F002I12-N4000 Aptina安森美ON工业相机14.0MP1400万像素COMS图像传感器
2020-12-05 20:06:22
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1/2.3-Inch 14MP CMOS Digital Image Sensor : MT9F002I12-N4000 :11.4° CRA HiSPi 48-pin iLCC

 
特性
•采用1.4μm像素的Aptina™A-Pix技术
•简单的二线串行接口
•自动黑电平校准
•支持60帧/秒的全高清视频性能
•20%的额外图像阵列区域在全高清,以支持电子图像稳定(EIS)。
•支持外部机械快门
•支持外接LED或氙气闪光灯
•高帧率预览模式与任意缩小大小从最大分辨率
•可编程控制:增益、水平和垂直消隐、帧大小/速率、曝光、左右和上下图像反转、窗口大小和平移
•数据接口:并行或四车道串行高速像素接口(HiSPi™)差分信令(SLVS)
•芯片锁相环(PLL)振荡器
•拜耳模式缩小标度器
 
应用
•数字摄像机
•静态数码相机
•工业相机
•电子显微镜
 
一般的描述
Aptina MT9F002是一款1/2.3英寸CMOS有源像素数字成像传感器,有源像素阵列为4608H x 3288V (4640H x 3320V包括边框像素)。它可以支持1400万像素(4384H x 3288V)的数字静态图像和1080p外加20%像素
用于数字视频模式下的电子图像稳定(4608H x 2592V)。MT9F002传感器是可编程的
通过简单的双线串行接口,并具有低功耗。
 
订购信息
表1:可用部件编号
型号                                      描述
MT9F002I12STCV    : 0° CRA HiSPi 48 pin iLCC
MT9F002I12STCU    : 0° CRA平行48 pin iLCC
MT9F002I12-N4000 : 11.4° CRA HiSPi 48 pin iLCC
MT9F002I12-N4003 :11.4° CRA平行48 pin iLCC
MT9F002I12-N4001 : 25° CRA HiSPi 48 pin iLCC
MT9F002I12-N4002 : 25° CRA平行48 pin iLCC
MT9F002D00STC    : C2EBC1裸片
 
一般的描述
MT9F002数字图像传感器采用Aptina突破性的低噪声CMOS成像技术,可以实现接近ccd的图像质量(基于信噪比和低光灵敏度),同时保持CMOS固有的尺寸、成本和集成优势。
当运行在它的默认4:3静止模式,传感器产生一个完整的分辨率(4384x3288)图像在13帧每秒(fps)使用HiSPi串行接口。芯片上的模数转换器(ADC)为每个像素生成一个12位的值。
 
功能概述
MT9F002是一种渐进扫描传感器,以恒定的帧速率生成像素数据流。它使用一个芯片,锁相环(PLL)产生所有内部时钟从一个主输入时钟运行在2到64兆赫。串行HiSPi I/F的最大输出像素率为220 Mp/s,并行I/F的最大输出像素率为96 Mp/s,对应的像素时钟速率分别为220 MHz和96 MHz。传感器的框图如图1所示。
传感器的核心是一个14Mp的有源像素阵列。定时和控制电路序列通过阵列的行,重新设置,然后依次读取每一行。在重置行和读取行之间的时间间隔内,行中的像素集成入射光。通过改变复位和读出之间的时间间隔来控制曝光。一旦一行被读取,从列的数据被排序通过一个模拟信号链(提供偏移校正和增益),然后通过ADC。ADC的输出是数组中每个像素的12位值。ADC输出通过一个数字处理信号链(提供进一步的数据路径校正并应用数字增益)。像素阵列包含光学活性和光屏蔽(“黑暗”)像素。暗像素被用来为芯片上的偏移校正算法(“黑电平”控制)提供数据。
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Features
• Aptina™ A-PIX technology with 1.4 μm pixels
• Simple two-wire serial interface
• Auto black level calibration
• Full HD support at 60 fps for maximum video performance
• 20 percent extra image array area in full HD to enable electronic image stabilization (EIS).
• Support for external mechanical shutter
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary downsize scaling from maximum resolution
• Programmable controls: gain, horizontal and vertical blanking, frame size/rate, exposure, left–right and top–bottom image reversal, window   size, and panning
• Data interfaces: parallel or four-lane serial highspeed pixel interface (HiSPi™) differential signaling (SLVS)
• On-chip phase-locked loop (PLL) oscillator
• Bayer pattern downsize scaler
 
Applications
• Digital video cameras
• Digital still cameras
• Industrial cameras
• Electron microscope
 
General Description
The Aptina MT9F002 is a 1/2.3-inch CMOS active-pixel digital imaging sensor with an active pixel array of 4608H x 3288V (4640H x 3320V including border pixels). It can support 14-megapixel (4384H x 3288V) digital still images and a 1080p plus additional 20 percent pixels
for electronic image stabilization (4608H x 2592V) in digital video mode. The MT9F002 sensor is programmable
through a simple two-wire serial interface, and has low power consumption. 
 
Ordering Information
Table 1: Available Part Numbers
Part Number                  Description
MT9F002I12STCV   : 0° CRA HiSPi 48-pin iLCC
MT9F002I12STCU   : 0° CRA Parallel 48-pin iLCC
MT9F002I12-N4000 : 11.4° CRA HiSPi 48-pin iLCC
MT9F002I12-N4003 :11.4° CRA Parallel 48-pin iLCC
MT9F002I12-N4001 : 25° CRA HiSPi 48-pin iLCC
MT9F002I12-N4002 : 25° CRA Parallel 48-pin iLCC
MT9F002D00STC : C2EBC1 Bare die
 
General Description
The MT9F002 digital image sensor features Aptina’s breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.
 
When operated in its default 4:3 still-mode, the sensor generates a full resolution (4384x3288)image at 13 frames per second (fps) using the HiSPi serial interface. An on-chip analog-to-digital converter (ADC) generates a 12-bit value for each pixel.
 
Functional Overview
The MT9F002 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 2 and 64 MHz. The maximum output pixel rate is 220 Mp/s for serial HiSPi I/F and 96 Mp/s for parallel I/F, corresponding to a pixel clock rate of 220 MHz and 96 MHz, respectively. A block diagram of the sensor is shown in Figure 1.
 
The core of the sensor is a 14Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel array contains optically active and light-shielded (“dark”) pixels. The dark pixels are used to provide data for on-chip offset-correction algorithms (“black level”control).

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