登录 / 注册
S2L55M安霸Ambarella集成系统芯片平台SoC,用于进阶型网络监控摄像机IP CAMERA,600Mhz ARM Cortex-A9 CPU和一个高性能数字信号处理(DSP)子系统、1个图像传感器管道
2021-06-29 20:56:44
点击购买/BUYamazon

SUMMARY DESCRIPTION
The S2L55M is an integrated system-on-achip (SoC) platform that targets IP cameras for advanced consumer/cloud 3Mp30 surveillance applications with HDR support.
S2L55m chips provide a 600-MHz ARM Cortex-A9 CPU and a high-performance digital signal processing (DSP) subsystem with an image sensor pipeline (ISP) and a high-definition (HD) H.264 codec engine. 
 
KEY FEATURES
※  Embedded ARM Cortex-A9 600-MHz CPU with L2 cache
※  More than 240 MPixel/s processing rate 
    ◎ 5-MPixel maximum sensor resolutior
※  Lens distortion correction for wide-angle lenses 
※  Wide Dynamic Range (WDR) image processing 
※  High Dynamic Range (HDR) engine with multiexposure fusion
※  3D noise reduction (Motion Compensated Temooral Filter, or MCTF)
※  Н.264 BP/MP/HP Level 4.1 and MJPEG codecs 
※  Maximum encode resolution: 5 Mpixels 
※  Support for Ambarella SmartAVC low bitrate streaming
※  256-pin, 0.65-pitch TFBGA package (11 mm x 11 mm)
※  28-nm CMOS Low Power (LP) technology 
※  Operating temperature from 0℃ to 70 ℃
 
1. OVERVIEW
This preliminary datasheet for the S2L55M processor from Ambarella begins with a brief introduction to the chip (Section 1.1) and a summary of key features (Section 1.2). Chapter 2 describes the S2L55m peripheral interfaces. For pin details and electrical characteristics refer to Chapter 3 and Chapter 4, respectively. See Chapter 5 for package information and Chapter 6 for Ambarella contact and ordering details.
Please note that the chip features described in this datasheet are subject to change. Details that have not been entirely finalized (e.g., encoding specifics) are provided using conservative estimates (i.e., final encoding performance is expected to meet or exceed the estimate provided).
 
1.1 Introduction
The S2L55M is an integrated system-on-a-chip (SoC) platform that targets IP cameras foradvanced consumer/cloud 3Mp30 surveillance applications with HDR support, including telco operator applications and cloud storage services for residential-evel applications. S2L55m chips provide a single-core Cortex-A9 ARM CPU and a high-performance digital signal processing (DSP) subsystem with an image sensor pipeline (ISP) and a high-definition (HD) H.264 codec engine. A functional block diagram of the S2L55m SoC is provided below .
S2L55M 安霸Ambarella 集成系统芯片平台SoC,进阶型网络监控摄像机IP CAMERA 600Mhz ARM Cortex-A9 CPU 高性能数字信号处理(DSP)子系统、图像传感器管道(ISP) 高清H.264编解码引擎 codec engine
 
The S2L55M SoC provides a glueless interface to Serial SLVS. HiSPi, and MIPI interfaces, as well as paralle connections to popular CMOS image sensors. The ISP offers advanced image-processing features including improved high dynamic range (HDR) processing with multi-exposure fusion, wide dynamic range (WDR) singleexposure tone mapping with local contrast enhancement, 3D noise reduction (Motion Compensated Temporal Filter, or MCTF), and geometric lens correction (for wide-angle lenses).
The H.264 codec engine delivers versatile encoding up to 3Mp30 total performance, including up to four simul taneous encode streams and support for up to 5 MP H.264 and 5 MP JPEG. The high-efficiency H.264 encoder supports SmartAVC, as well as advanced Main and High-Profile functions for the highest-quality and lowest possible bitrate. These functions include bidirectional prediction (B-frames), large motion-estimation search range, and macroblock-level quantization. Ambarella builds in flexibility with a multi-streaming function (up to four streams), allowing on-the-fly start/stop as well as the adjustment of the bitrate, frame rate, and GOP of each individual stream
A 600-MHz ARM Cortex-A9 CPU with NEON DSP extensions and floating point support is available for implementing full-featured user applications.   
 
The S2L family is fabricated using low-power 28-nm CMOS technology and integrates advanced power-saving modes, such as utilizing DSP-subsystem memory resources to reduce external memory bandwidth and total camera system power requirements. The S2L evaluation kit (EVK) and software development kit (SDK) provide a Linux-based framework and development environment that includes demonstration applications, source code image-tuning tools, and a rich set of APls that expose the DSP imaging and codec functionality at the ARM level enabling a range of product customization and differentiation options. 
 
1.2 Feature List
Features of the S2L55m chip include:
※  Embedded ARM single-core Cortex-A9 CPU
   ◎   Clock frequency up to 600 MHz
   ◎   32-KByte data/ 32-KByte instruction cache 
   ◎   128-KByte L2 cache
   ◎   NEON SIMD engine
   ◎   Floating Point Unit (FPU)AES/3/DES/SHA-1/MD5 encryption engine
 
※  DR3 and DDR3L controller
   ◎   Up to 528-MHz clock rate
   ◎  16-bit wide data bus
   ◎   Maximum capacity of 2 Gbits (256 MBytes) 
 
※  Image pipeline
   ◎   More than 240 MPixel/s processing rate 
   ◎   5-MPixel maximum sensor resolution
   ◎   Geometric lens correction (for wide-angle lenses) 
   ◎   Black level correction
   ◎   Dynamic and static defect pixel cluster correction
   ◎   RGB Bayer demosaicing
   ◎   Lens shading correction
   ◎   3D LUT color transform with gamma
   ◎   Wide Dynamic Range (WDR) single-exposure tone mapping
   ◎   High Dynamic Range (HDR) engine with multi-exposure fusion
   ◎   3D noise reduction (Motion Compensated Temporal Filter, or MCTF)
   ◎   Flexible APls and image-tuning tools
   ◎   Adjustable 3A; exposure, white balance and focus control (AE/AWB/AF)
   ◎   RGB and YUV statistics, histogram and AF focus value generation
   ◎   Luma sharpen and chroma noise filter
   ◎   Four resizers (1/16x to 8192x scaling) with digital pan, tilt and zoom (PTZ) 
   ◎   Crop, mirror, flip, 90°/270° rotation
   ◎   Alpha-blending OSD up to full-frame overlay for text, image and privacy mask 
 
※  Video engine
   ◎   Maximum encode resolution: 2592x1944
   ◎   H.264 BP/MP/HP Level 4.1 and MJPEG codecs।
   ◎   Encode performance up to 3Mp30 with four flexible streams
        - Up to four real-time simultaneous encodes with on-the-fly start/stop as well as the adjustment of the bitrate, frame rate, and GOP of each individual stream
   ◎   Advanced H.264 compression tools
        - I, IP, IBP modes (M=1,2,3; IP, IBP, IBBP)
        - SVCT Scalable Video Coding
   ◎    Flexible rate control
        - SmartAVC ultra-low bitrate H.264 streaming
        - CBR. VBR and Constant QP with max bitrate control
        - Macroblock-level adaptive quantization
   ◎   Dynamic ROl encoding with unrestricted number of free-form areas at macroblock boundary 
 
※  Sensor/Video Input (VIN) interface
   ◎   Multiple input modes
        - Supports up to 8-lane SLVS/HiSPi input
        - Supports up to 4-lane MIPI input
        - Support for 14-bit parallel and LVCMOS sensors
   ◎  Support for popular CMOS sensors; Aptina, Sony, OV, Panasonic
   ◎  16-bit CCIR.601 video input with external sync signals
   ◎   8-bit, 10-bit, 12-bit or 14-bit BT.656 video input with embedded sync codes including full-data range support
※   Video Output (VOUT) interfaces
   ◎   Two video output ports
        - One logical channel drives analog
        - One logical channel drives digita
   ◎   Popular LCD panel controllers (RGB mode)
   ◎   Support for RGBA and YUVA OS
   ◎   DVideo DAC for 480i/576i composite PALNTSC output
   ◎   BT. 656 embedded sync YUV output (8-bit or 16-bit mode)
※   AHB Bus DMA controller
   ◎   Memory-to-memory transfers including support for transfers between memory and peripherals 
   ◎   Programmable transfer count up to 4 MB
   ◎   DMA scatterlaather via chained descriotor list in memory with DMA control information source 
※   Dedicated DMA co-processor for graphics and image operations
   ◎   Offers linear copy, 2-D copy, composite, and alpha-blend image operations
   ◎   Supports 4- to 32-bit pixel formats
※   12S digital audio interface (stereo)
   ◎   Audio record/playback
※   Ethernet MAC controller
   ◎   IEEE 802.3 compliant with full- and half-duplex(IEEE 802.3x low-control) and Jumbo frames
   ◎   IEEE 802.3xEEE 802.1Q VLAN tag detection
   ◎   Checksum offi-load for received IP and TCP/UDP packetshtrol) and Jumbo frames
   ◎   Dedicated pins for RMIl or MIll interface
   ◎   FIFO (2 KB /2 KB) and DMA support
※  One USB 2.0 interface
   ◎   One port configurable as host or device, with built-in PHY
※   Flexible Storage Media Input / Output (SMIO) interface
   ◎   NAND Flash controller
        - Up to 8-Gbit device, 512-Byte and 2-KByte page sizes
        - 8-bit flash chip data bus
        - 4-bit and 8-bit SLC with ECC hardware and read-confirm support
        - BCH error correction and increased spare area available
※   One SD controller (SDO)1
   ◎   bit, 4-bit SD modes, CRC7 for command and CRC16 for data integrity
※   Multiple boot options
   ◎   SPI-NOR, NAND Flash, USB and eMMC
※   Vector interrupt controller including VIC CPU-offload functionality
※   SSI/ SPI controller interfaces
   ◎   Two SSI/ SPI masters with up to seven device enables
   ◎   One dedicated SSI/ SPI slave port to connect to an external system master
※   Two-wire serial Inter-Integrated Circuit (IDC) interfaces (x2)
   ◎   Configurable IDC buses
※   UART interfaces (x2)
※   Up to 76 General Purpose Input/Output (GPIO) short-height pins with individual pull-up/down control
※   ADC (two channels) with high/low threshold interrupt generation and 12-bit resolution
※   Built-in power controller for power-up/down sequencing
※   Real Time Clock (RTC)
※   Interval timing with eight general-purpose timers confiqurable as external event counters
※   Watchdog timer (one)
※   One Pulse Width Modulator (PWM)
※   JTAG In-Circuit Emulator (ICE) interface for debugging (one)
※   256-pin.  0.65-pitch TFBGA package (11 mm x 11 mm)
※   28-nm CMOS Low Power (LP) technology
※   Operating temperature from 0 ℃ to 70 ℃
 
 
 
 
概要描述
S2L55M是一种集成的系统芯片(SoC)平台,用于高级消费者/云3Mp30帧监控应用的IP摄像头,并支持HDR。
S2L55M芯片提供一个600Mhz ARM Cortex-A9 CPU和一个高性能数字信号处理(DSP)子系统、一个图像传感器管道(ISP)和一个高清H.264编解码引擎。
 
关键特性
※  嵌入式ARM Cortex-A9 600-MHz CPU,具有L2缓存
※  超过240 MPixel/s的处理速度
    ◎5-MPixel最大传感器分辨率
※  广角镜头的镜头畸变校正
※  宽动态范围(WDR)图像处理
※  高动态范围(HDR)发动机,多曝光融合
※  3D降噪(Motion Compensated Temooral Filter, MCTF)
※  Н.264BP/MP/HP Level 4.1和MJPEG编解码器
※  最大编码分辨率:500万像素
※  支持Ambarella SmartAVC低比特率流媒体
※  256pin, 0.65 间距 TFBGA封装(11mm x 11mm)
※  28nm CMOS低功耗技术
※  工作温度从0℃到70℃
 
1. 概述
这是Ambarella S2L55M处理器的初步数据,首先是对芯片的简要介绍(第1.1节)和关键特性的总结(第1.2节)。第2章介绍S2L55m外设接口。引脚细节和电气特性分别参见第3章和第4章。参见第5章包装信息和第6章Ambarella联系和订购细节。
请注意,本数据表中描述的芯片特性可能会发生变化。未完全确定的细节(例如,编码细节)使用保守估计(即,最终编码性能预期满足或超过提供的估计)提供。
 
1.1介绍
S2L55M是一个集成的片上系统(SoC)平台,以IP摄像头为目标,用于高级消费者/云3Mp30监控应用,并支持HDR,包括电信运营商应用和住宅级应用的云存储服务。S2L55M芯片提供一个单核Cortex-A9 ARM CPU和一个高性能数字信号处理(DSP)子系统、一个图像传感器管道(ISP)和一个高清H.264编解码引擎。S2L55M SoC的功能框图如下所示。
 
1.2特性列表
S2L55M芯片的特点包括:
※  嵌入式ARM单核Cortex-A9处理器
    ◎时钟频率可达600mhz
    ◎32kbyte数据/ 32kbyte指令缓存
    ◎128kbyte L2缓存
    ◎霓虹SIMD发动机
    ◎FPU (Floating Point Unit)AES/3/DES/SHA-1/MD5加密引擎
※  DR3和DDR3L控制器
    ◎时钟频率可达528-MHz
    ◎16位宽数据总线
    ◎最大容量2gbits (256mb)
※  形象、管道
    ◎240 MPixel/s以上的处理速度
    ◎5-MPixel最大传感器分辨率
    ◎几何镜头校正(广角镜头)
    ◎黑电平校正
    ◎动态、静态缺陷像素聚类校正
    ◎RGB拜耳马赛克
    ◎镜头遮光校正
    ◎3D LUT颜色变换与伽玛
    ◎宽动态范围(WDR)单曝光色调映射
    ◎高动态范围(HDR)发动机,多曝光融合
    ◎3D降噪(Motion Compensated Temporal Filter,简称MCTF)
    ◎灵活的apl和图像调节工具
    ◎3可调;曝光、白平衡和聚焦控制(AE/AWB/AF)
    ◎RGB和YUV统计,直方图和对焦值生成
    ◎亮度锐化和色度噪声滤波
    ◎四个调整器(1/16倍至8192x缩放),具有数字平移、倾斜和缩放功能(PTZ)
    ◎裁剪,镜面,翻转,90° /270°旋转
    ◎alpha混合OSD到全帧覆盖文本,图像和隐私蒙版
※  视频引擎、
    ◎最大编码分辨率:2592x1944
    ◎H.264 BP/MP/HP Level 4.1 and MJPEG codecs।
    ◎编码性能高达3Mp30,四种灵活的流
      -多达4种实时同步编码,可实时启动/停止,并可调整每个单独流的比特率、帧率和GOP
    ◎先进的H.264压缩工具
      -I, IP, IBP模式(M=1,2,3;IP、IBP IBBP)
      -SVCT可伸缩视频编码
    ◎灵活的速率控制
      -SmartAVC超低比特率H.264流媒体
      -CBR。VBR和最大比特率控制恒定QP
      -宏块级自适应量化
    ◎动态ROl编码,在宏块边界无限制数量的自由形式区域
 
※  传感器/视频输入(VIN)接口
    ◎多种输入方式
      -最多支持8通道SLVS / HiSPi输入
      -最多支持4路MIPI输入
      -支持14位并行和LVCMOS传感器
    ◎支持流行CMOS传感器;Aptina,索尼,OV,松下
    ◎16位CCIR.601视频输入,外部同步信号
    ◎8位、10位、12位或14位BT.656视频输入,内置同步码,支持全数据范围
※  视频输出(VOUT)接口
    ◎2个视频输出接口
      -1个逻辑通道驱动模拟
      -1个逻辑通道驱动数字
    ◎流行LCD面板控制器(RGB模式)
    ◎支持RGBA和YUVA OS
    ◎DVideo DAC用于480i/576i复合PALNTSC输出
    ◎BT. 656嵌入式同步YUV输出(8位或16位模式)
※  AHB总线DMA控制器
    ◎内存到内存传输,包括支持内存和外设之间的传输
    ◎可编程传输数达4mb
    ◎DMA散射laather通过链式描述符列表在内存中与DMA控制信息源
※  用于图形和图像操作的专用DMA协处理器
    ◎提供线性复制、二维复制、合成和阿尔法混合图像操作
    ◎支持4 ~ 32位像素格式
※  12S数字音频接口(立体声)
    ◎音频记录/回放
※  以太网MAC控制器
    ◎兼容IEEE 802.3全双工和半双工(IEEE 802.3低控制)和Jumbo帧
    ◎IEEE 802.3xEEE 802.1Q VLAN tag检测
    ◎接收IP和TCP/UDP报文的校验和offi-load)和Jumbo帧
    ◎ril或MIll接口专用引脚
    ◎FIFO (2kb / 2kb)和DMA支持
※  1个USB 2.0接口,
    ◎1个端口,可作为主机或设备配置,内置PHY
※  灵活的SMIO (Storage Media Input / Output)接口
    ◎NAND Flash控制器
      -最大8gbit设备,512-Byte和2-KByte页面大小
      -8位flash芯片数据总线
      -4位和8位SLC ECC硬件和读取确认支持
      -BCH错误纠正和增加可用的空闲面积
※  1个SD控制器(SDO)
    ◎1位,4位SD模式,CRC7命令和CRC16的数据完整性
※多个启动选项
    ◎SPI-NOR, NAND Flash, USB和eMMC
※  矢量中断控制器,包括VIC, CPU卸载功能
※SSI/ SPI控制器接口
    ◎2个SSI/ SPI master,多达七个器件使能
    ◎1个专用SSI/ SPI从端口,用于连接外部系统主机
※  IDC (two - line serial Inter-Integrated Circuit)接口(x2)
    ◎IDC总线可配置
※  UART接口(x2)
※  多达76个通用输入/输出(GPIO)短高度引脚,具有独立的上/下拉控制
※  具有高/低阈值中断产生和12位分辨率的ADC(两个通道)
※  内置电源控制器,实现上/下电顺序
※  实时时钟(RTC)
※  使用8个可配置为外部事件计数器的通用计时器进行间隔计时
※  看门狗定时器(1个)
※  1脉宽调制器(PWM)
※  用于调试的JTAG在线仿真器(ICE)接口(1个)
※  256 -pin,0.65间距,TFBGA封装(11毫米x 11毫米)
※  28nm CMOS低功耗技术
※  工作温度从0℃到70℃
S2L55M 安霸Ambarella 集成系统芯片平台SoC,进阶型网络监控摄像机IP CAMERA 600Mhz ARM Cortex-A9 CPU 高性能数字信号处理(DSP)子系统、图像传感器管道(ISP) 高清H.264编解码引擎 codec engine
S2L55M 安霸Ambarella 集成系统芯片平台SoC,进阶型网络监控摄像机IP CAMERA 600Mhz ARM Cortex-A9 CPU 高性能数字信号处理(DSP)子系统、图像传感器管道(ISP) 高清H.264编解码引擎 codec engine
S2L55M 安霸Ambarella 集成系统芯片平台SoC,进阶型网络监控摄像机IP CAMERA 600Mhz ARM Cortex-A9 CPU 高性能数字信号处理(DSP)子系统、图像传感器管道(ISP) 高清H.264编解码引擎 codec engine
 
 
有关S2L55M的价格,datasheet,简介,文档下载,原装现货,现货库存,芯片,图片,规格书,代理商,技术支持,产品介绍,参数,方案商,分销商,经销商,官网,生产厂家,专卖店,高价收购,模组,模块,特价,库存,生产商,哪里买,性价比,用途,均可联系本公司

上一篇/Previous posts:VC0338中星微Vimicro USB2.0摄像头处理器超小型BGA88主控
下一篇/Next chapter:OV538-B88,OV538-LB50,OV00538-B88G,Camera Bridge Processor,camera single-chip,USB2.0 camera system,suport 2MP camera,摄像机桥处理器单片机,集成USB 2.0摄像头系统